Reduced Power Flip Flop Design for Clock Distribution Networks

In this paper a technique is proposed to reduce the power consumption in clock distribution networks. Power has become a major issue in most VLSI designs. Power distribution in VLSI differs from product to product. However it is interesting to note that clock system and logic part itself consume most of total chip power. In practise a large portion of clock distribution network (CDN)s and flip flops. In this paper a reduced power flip flop design is used in CDNs. The simulations are done using Microwind and DSCH analysis software tools. Keywords— Flip-flop, full swing low swing, power, resonant clock